added support for LDR and models
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@@ -69,6 +69,7 @@ typedef enum
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channel_DAC1 = 0x3d,
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channel_FVR_BUF1 = 0x3e,
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channel_FVR_BUF2 = 0x3f,
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channel_ANA0 = 0x0,
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channel_ANC0 = 0x10
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} adc_channel_t;
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@@ -49,6 +49,25 @@
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#define PULL_UP_ENABLED 1
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#define PULL_UP_DISABLED 0
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// get/set IO_RA0 aliases
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#define IO_RA0_TRIS TRISAbits.TRISA0
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#define IO_RA0_LAT LATAbits.LATA0
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#define IO_RA0_PORT PORTAbits.RA0
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#define IO_RA0_WPU WPUAbits.WPUA0
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#define IO_RA0_OD ODCONAbits.ODCA0
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#define IO_RA0_ANS ANSELAbits.ANSA0
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#define IO_RA0_SetHigh() do { LATAbits.LATA0 = 1; } while(0)
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#define IO_RA0_SetLow() do { LATAbits.LATA0 = 0; } while(0)
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#define IO_RA0_Toggle() do { LATAbits.LATA0 = ~LATAbits.LATA0; } while(0)
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#define IO_RA0_GetValue() PORTAbits.RA0
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#define IO_RA0_SetDigitalInput() do { TRISAbits.TRISA0 = 1; } while(0)
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#define IO_RA0_SetDigitalOutput() do { TRISAbits.TRISA0 = 0; } while(0)
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#define IO_RA0_SetPullup() do { WPUAbits.WPUA0 = 1; } while(0)
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#define IO_RA0_ResetPullup() do { WPUAbits.WPUA0 = 0; } while(0)
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#define IO_RA0_SetPushPull() do { ODCONAbits.ODCA0 = 0; } while(0)
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#define IO_RA0_SetOpenDrain() do { ODCONAbits.ODCA0 = 1; } while(0)
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#define IO_RA0_SetAnalogMode() do { ANSELAbits.ANSA0 = 1; } while(0)
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#define IO_RA0_SetDigitalMode() do { ANSELAbits.ANSA0 = 0; } while(0)
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// get/set IO_RA2 aliases
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#define DEBUG_TRIS TRISAbits.TRISA2
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#define DEBUG_LAT LATAbits.LATA2
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